1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more specifically, to a clamp circuit utilized in read-only-memory (ROM) devices.
2. Technical Background
A semiconductor ROM device is composed of a number of memory cells which are formed by intersecting a plurality of word lines and bit lines on a semiconductor substrate. As the on/off states of the memory cells have been determined in their manufacturing processes, the data stored therein will not fade away and can be read out by specific sensing circuits. Therefore, the ROM devices are provided for electronic instruments in which nonvolatile data storage is required, i.e., the data must be lossless even if no electrical power is supplied.
Among all ROM device structures, the so-called "flat-cell" ROM structure is the most popular one. Since the large-area which consumes field oxide layers can be eliminated from the flat-cell structure, the cell density can be greatly increased. FIG. 1 is a schematic diagram illustrating a flat-cell memory bank structure. The bank structure shown in FIG. 1 includes a number of word lines W.sub.L1 through W.sub.LN, sense-amplify signal lines SA1 and SA2, virtual ground lines VG1 and VG2, metal bit lines MBL1 through MBL3, and a memory cell array consisting of cells A-D and J-M etc. Moreover, in order to form a data read path to the memory cells, bank select lines S.sub.N and S.sub.N+1 are provided for controlling transistor switches T1-T7.
The aforementioned ROM device has its word lines, bit lines and other signal lines applied with specific voltages to choose a memory cell in the memory cell array, and data is then read through the sensing circuit. For example, in order to readout the data stored in cell A, the voltage level of bank select line S.sub.N is high, S.sub.N+1 is low, and virtual ground line VG1 is biased through a column control pass gate by low voltage source VSS. Therefore, transistor switches T1 and T4 are turned on and switches T3, T6 and T7 are turned off. Since virtual ground line VG2 is biased to a level equivalent to that of sense-amplify bit line SA1, transistor switches T2 and T5 are turned on but with very little current flow therethrough. Therefore, the read operation of the cell is not affected. Accordingly, the current amplitude of the data read path consisting of transistors T1, T4 and cell A can be sensed to determine the data stored in cell A.
The current in sense-amplify bit line SA1 can be read out, through metal bit line MBL2, by a sense amplifier, such as the conventional sense amplifier illustrated in FIG. 2A. However, if cells B and D are also turned on when cell A is accessed, parasitic capacitance C3, C4 and C5 of the bit line will share charges with capacitance C1 and C2, thus affecting the read operation of cell A. Therefore, a clamp circuit, such as that shown in FIG. 2B, has to connect with bit line MBL3 to provide a constant voltage and reducing the charge sharing effects of parasitic capacitance C3, C4 and C5.
Referring to FIG. 2B, the conventional clamp circuit includes active load MP2, NOR gate 20, NMOS transistor MN21, and another NMOS transistor MN22. Connected with active load MP2, transistor MN 21 is controlled by NOR gate 20. NOR gate 20 has two input ends. One is controlled by chip select signal CS for disabling the clamp operation, and the other is connected to the connection point of the two transistors MN21 and MN22. Transistor MN22 is a pass gate for providing voltage to bit line MBL3 under the control of column select signal YG.
In order to increase the area of metal contact windows, any two adjacent contacts of the metal bit lines and the sense-amplify bit lines (or virtual ground bit lines) are arranged at opposite ends of the memory bank. For example, referring to FIG. 1, since sense-amplify bit line SA1 and metal bit line MBL2 connect at the upper end of the bank, virtual ground line VG2 has to connect metal bit line MBL3 at the lower end of the bank. Moreover, since the sense-amplify bit lines and virtual ground bit lines are substantially diffusion regions, their effective resistance depends on the length of data path. Therefore, as two different cells in the same bank have different data paths, their corresponding effective resistance may also differ with respect to each other.
Referring to the reduced memory bank structure shown in FIG. 3, wherein a number of cells A, B, C, D, K and L are included. When bank select line S.sub.N+1 has a high level voltage, word line W.sub.L1 is high, virtual ground bit line VG1 connects to a low voltage source VSS, and VG2 connects to the clamp circuit of FIG. 2B, a data path to cell B is formed. If cell C is also turned on, charges in parasitic capacitance C4 must be balanced by the clamp circuit through virtual ground line VG2, especially when cell B is a normally off cell. Alternatively, when word line W.sub.L1 becomes low and word line W.sub.L32 becomes high, another data path to cell K is formed. If cell L is also turned on, the charge sharing effect of capacitance C4 has to be eliminated by the clamp circuit through VG2. However, since cells C and L locate at opposite ends of the memory bank, they have different path lengths to the clamp circuit. Therefore, the voltages are provided from the clamp circuit to offset the capacitance variation due to the variation of effective resistance in virtual ground line VG2. Since the parasitic capacitance cannot be uniformly offset, the voltage variation of the clamp circuit affects the performance of the ROM device.